Many integrated circuit chips, particularly memory chips, are being manufactured with two power supply voltages: the standard VCC voltage for powering the core electronics of the chip, and a second voltage VCCQ for powering the output drivers (also called output buffers) of the chip. The output drivers convey the chip's output signals to other chips of the digital system in which the chip is placed, and draw a large amount of current and power to do so. The switching of the output drivers can generate relatively large current and voltage spikes on the power supply and return lines. For this reason, output drivers are typically designed to have controlled rise and fall slew times so that they do not switch logic states too quickly. Because the magnitudes of the current and voltage spikes are proportional to the slew times, controlling the slew times will control the magnitudes of the spikes.
Using a separate supply voltage VCCQ for the output drivers has at least two advantages. First it enables one to use different external bypass capacitors for the two supplies VCC and VCCQ, which helps to isolate the current and voltage spikes from the core of the integrated circuit. Second, it enables one to adjust the output voltage levels of the chip to match those of the digital system without the use of special interface circuitry. As in known in the art, the electronics industry is using a wide variety of supply voltages for digital circuits, ranging from 1.5 V to 5 V, with 2.5V and 3.3 V being popular choices. Memory devices are used in a wide variety of applications, which are powered by a wide range of voltages. Often it is found that the speed performance of a memory device works well at a particular voltage, which may or may not be the same as the voltage used by the rest of the digital system. The second VCCQ supply enables the circuit designer to provide the core of the memory device with the voltage that optimizes its performance through the VCC pin, and to provide the output drivers with the voltage that interfaces with the rest of the digital system through the VCCQ pin.
However, part of the overall speed performance of a memory device (or other digital circuit chip) is dependent upon both the speed performance of the chip's core circuits and the rising and falling slew times of the output drivers. In current chip designs, these slew times are highly dependent upon the value of the VCCQ voltage. And thus, a circuit designer is constrained to a limited range of VCCQ if he wants to achieve optimal speed performance from the chip.